The Final Task

This week is my last week of work as a part time engineer. I focused on the previous task that had been given, which is to develop a simple Verilog design. The Final Task Since...

Documentation for Project

This week has been spent mainly on documentation of the previous work that had been done. Simplify Code Documenting the code is reminding myself on why do I write it in the way at...

Search for System Bugs

This week, I continued with my previous week task, to find the way on how SPI C code actually work with the Verilog module. I stared on the same circuit for hours, but then...

Analyze the Inferred HDL

This week, I have been working on the GPIO address and the C++ code. Previously, an assumption that had been made for the address of the GPIO registers, which are the control register and...

BRAM Size before Synthesis

This week continues with the issue that I had opened previously, which is on the issue that some file is not updated before the synthesis starts. This was a mistake made by the previous...

Discover More Bugs

This week  the task is very time consuming, because I spent most of the time debugging and reading the logs in the terminal. As I got to know from my colleague Jeunn Hao, that...

Fixing Simulator Bug

This week, I have been working mainly on the simulator. Things just don’t work when they are combined 😂 😂 , especially when it is a combination of 3 persons code. It is a critical issue that...

Kill the Zombie

This week, my task is to create a cache system for the FPGA synthesis and implementation process, and to kill the previous synthesis process. The cache system would be useful if someone replicates or...

Automate Bitstream: Part 3

Continued from last week, I finally manage to automate the bitstream generation. Good news that I have also fixed the problem that causes the hanging of the web application. The hanging is mainly caused...