Memory Mapped I/O and Port-Mapped I/O

Completion of Timer Interrupt

This week, I had been working around with the timer interrupt, confirmed that the timer interrupt mechanism is actually correct after storing and restoring the 32 general registers that had been discussed previously. RISC-V control status register ISA only works around with the registers, but not the immediate value. Thus, I had to save an immediate value to a register before using the control status register ISA such as CSRRW, CSRRS, and etc. Configuring most of the instruction such as store and restore in the C/C++ code actually makes me understand more about the control and status register of RISC-V, and it does not involve any modification on the RISC-V Angel code.

The Memory Mapped I/O and Port-Mapped I/O

Initially, I had a discussion with my colleague Islam and Sumia, about how to communicate between the code editor and the simulator. Our final aim is to make a simple GPIO module to output HIGH and LOW correctly. Although the discussion went well, and I also found a library from previous intern. By doing some minor modification to the library, I changed the address of the GPIO module into the RAM of the simulator. Eventually as the work progressing, I found another issue when my colleague Sumia came to ask me about the memory mapped that she wanted to do. And the issue was the hardware processor that is going to be implemented is using a Port-mapped I/O instead of a memory-mapped I/O, in which what I had been doing was for the memory mapped I/O.

Memory mapped I/O and Port-mapped I/O actually makes a huge difference in development of the simulator. As I would need to understand the type of I/O mapping, and to design the algorithm to port it to the simulator. I had read a lot about the difference between memory mapped I/O and port-mapped I/O. The biggest concern was the port-mapped I/O may have the same addresses as the instruction addresses. In order to switch between the port, there might be a special instruction needed to switch the port to control the I/O. Besides, there are many difference way to achieve this, and hopefully I might found some useful ideas from other simulator engines next week.

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