Building Verilog Modules

Time flies by so fast, I can not believe that we almost approach the mid of the internship !! .. By writing this blog entry I can say that I have successfully completed 12 weeks .. 12 weeks that were full of knowledge, stress, hardworking and sometimes …. fun 😀 .

This week my task was completion of the past weeks work. I had to start writing the verilog module definitions for different components and devices. These modules will then be later instantiated in the top level modules and get connected to the processor for communication. Each component can have one or more serial communication interfaces such as I2C, UART, SPI and GPIO. So in order for the user later to get these devices to communicate with the board. Some board pins have to be programmed as I2C or any other interfaces. The definition of all the I2C, UART and …etc have been already written and all what I had to do was to instantiate these modules in the verilog module definition of these components. For example, the first component I was working in was called “9 degree of freedom stick”. The device has only slave I2C interface so inside the module definition I just instantiated the master I2C module . for the second component  “SPI Flash memory ” the case was pretty different. Building the module definition of this device was a bit hard as the device has two different communication interfaces which requires to instantiate both modules, one to deal with GPIO pins and the other with the SPI. A switch or a decoder is then needed to select which module to select based on certain bits on the addresses that comes from the processor.

During working on writing the verilog module definitions of different components I realized that the user has the ability to adjust and change some parameters of the interfaces from the C++ code like the speed and the frequency of the clock in the I2C communication. The user can not set these values arbitrarily. He should follow the protocol specification and the allowed values written in the data-sheet of these devices. So I was thinking of a way to validate the values the user enters when he declares the respective classes of these modules in the C++ code, the best stage to get the inputs validated was to me before the creation of the top level module. The user should also be notified that he enters invalid values by using similar way of notifying him/her by the syntax errors in the C++ code. On way was to use the classes constructor to test the validity of the user entry using assert function or just simple if statement that does the checking and then abort the program or write out some error messages . But this type of testing requires the program or the code of the user to be run or executed at least once which may be undesirable. Other way was to use the list that is created for the schematic editor .The list contains all the components that the user declares in the C++ with their IDs and all other parameters. Then from this list we can extract the information of the parameters like the speed and the frequency and do the checking.

For next week, I have to modify the code that creates the verilog top level module in order to be able to set the parameters of different components. Previously I didn’t pay attention to this point because we were only using one component that has only one parameter, but then as we keep adding more components , the complexity increases. The number of parameters for each component is not fixed and it depends on the number of interfaces it has. So I really have to come up with smart way to set those values without requiring to check what interface  this component has.

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