Gitosis and Github

We have our own gitosis server running in our office server. We’ve typically used this to work on private projects. The problem with this setup is that there was not direct link between the office gitosis server with our repositories on github.

This problem has now been solved and we’re currently using our office gitosis server as a middle-layer repository. The gitosis server acts also as a downstream repository for our github repositories.

This can be easily done by logging into the gitosis server as the gitosis user and doing the following.

$ cd $HOME/repositories
$ git clone --bare [email protected]:aeste/sandbox.git

This will create a bare repository that can be pushed to and pulled from.

For existing repositories, the key would be to add the github repositories as upstream origin repositories.

$ cd $HOME/repositories/sandbox.git
$ git remote add origin [email protected]:aeste/sandbox.git

This will link our existing repository to the upstream repository on github.

After making local changes on our workstations and pushing them to our gitosis server, we can push the same changes upstream to github by:

$ cd $HOME/repositories/sandbox.git
$ git push -u origin master
$ git push -u origin develop

If there are changes on the github server, these can be pulled downstream to the gitosis server by:

$ cd $HOME/repositories/sandbox.git
$ git pull -u origin master
$ git pull -u origin develop

Synchronisation! This could even be automated.

The main advantage to new current setup is the speed at which we can clone the repository as we are no longer limited by the internet line at the office but are now limited by the computational speed of the gitosis server.

Git SVN Workflow

For some of our projects, FreeRTOS specifically, we need to track a SVN upstream repository that is hosted on Source Forge. As we’re only interested in pulling upstream changes and not pushing anything upstream, this simplifies our workflow a bit.

The first thing that is needed is to configure the upstream SVN repository. In our case, we already have an existing git repository. Therefore, instead of cloning the actual SVN tree, we’ll only pull in the necessary changes.

$ cd freertos-port.git
$ git svn init -s https://freertos.svn.sourceforge.net/svnroot/freertos

Fetching the entire SVN history would take ages. Therefore, we’re limiting the fetch to only the more recent releases (r1611 onwards). This operation will take a little time. Time to grab a coffee break.

$ git svn fetch -r 1611:HEAD

Next, we need to merge in the upstream code. We only work of stable upstream releases, which are tracked as specific SVN branches. This can be done by merging the remote branches directly.

$ git branch -a
$ git checkout develop
$ git merge remotes/tags/V7.0.2

Periodically, new code needs to be pulled from the upstream repository. This will only be done to track a new stable upstream release. This can be accomplished using the following method:

$ git svn fetch
$ git checkout develop
$ git branch -a
$ git merge remotes/tags/V7.1.0

Otherwise, we use git-flow as usual. Once things are done, push any changes up to github.

$ git push -u origin master
$ git push -u origin develop

Git Upstream Ports

We’ve recently added a number of git repositories at github to track ports of various software tools to our platform. These are the steps that we used to get things working. We will use the binutils port as an example.

Create
For consistency, we’ll name all our upstream code as upstream for obvious reasons.
Instead of tracking everything, it might be more beneficial to just track the upstream master branch as we only want to track the main development code.
To create the initial repository, these steps are used:

$ mkdir binutils-port.git
$ cd binutils-port.git
$ git flow init
$ git remote add upstream -t master git://sourceware.org/git/binutils.git
$ git remote add origin [email protected]:aeste/newlib-port.git
$ git push -u origin master
$ git push -u origin develop

Upstream
We would like to only work off stable releases.
Therefore, instead of merging the complete upstream branch, we’ll only merge in stable code tagged as official releases.
To fetch and merge stable upstream code, use these steps:

$ git fetch upstream
$ git fetch upstream --tags
$ git tag
$ git show-ref binutils-2_22
$ git checkout develop
$ git merge XXXXXXXX

Modifications
Use the standard git-flow model to make modifications to the code. To merge the code from future upstream stable releases:

$ git fetch upstream
$ git fetch upstream --tags
$ git tag
$ git show-ref binutils-X_XX
$ git checkout develop
$ git merge XXXXXXXX

Push
Once the code is ready it needs to be pushed up to github.
This should be done as and when necessary, particularly after major releases or hotfixes.
For this example, we’ll push up two public branches and a tag (12.02).

$ git push -u origin master
$ git push -u origin develop
$ git push origin 12.02

That’s it.

The Littlest Processor

I’ve always dubbed the AEMB as the littlest processor that could, after the famous book with an engine. To figure out just how little it is? It occupies less than 20% of the real-estate in the second smallest Spartan6LX9 FPGA.


Slice Logic Utilization:
Number of Slice Registers: 866 out of 11440 7%
Number of Slice LUTs: 1167 out of 5720 20%
Number used as Logic: 1035 out of 5720 18%
Number used as Memory: 132 out of 1440 9%
Number used as RAM: 132

Speed Grade: -3
Minimum period: 9.706ns (Maximum Frequency: 103.030MHz)

In a mid-range Spartan6LX45, it occupies an insignificant amount of on-chip real-estate. There is no doubt that this is the littlest processor that could.

FPGA families overview

Field Programmable Gate Array (FPGA) is a type of hardware/logic programmable integrated circuit. It’s flexibility, speed and the increasing number of IP cores make it into a popular solution in embedded system.

The selection of the FPGA core is important when designing a FPGA system. FPGA vendors divide their products into few groups. Each group targets different application such as high performance, mid-range, low cost and low power application. Furthermore, each product group can divide into few families. Every family have different features to support the target applications.

The parameters listed below are important when selecting a FPGA core for a system.,

- Logic Cells/Elements
- Block RAM
- Hard IP block (eg. memory controller and DSP block)
- I/O Pin
- I/O logic level
- Configuration method
- Power consumption
- Cost
- Avaibility
- Supported tools

Since the architecture of logic cells, block ram and DSP block architecture is different between families. Therefore the comparison are not straight forward. The synthesis tool and the logic block architecture may vary the number of logic elements that used by a design.

Most FPGA vendors don’t specify the total power consumption of each devices since it depends on the system design, frequency, and core voltage that used by the system. However, FPGA vendors offer power calculator/estimator that can roughly calculate the power consumption.

Price may vary with different distributer. It is difficult to conclude that which family provides the higher performance-price ratio. If the price is important, then try to contact local distributer to quote the price.

Some of the FPGA vendors and their families are listed below. All parameters are based on the maximum value from each family.

Xilinx
The company offers three SRAM based FPGA families that cover high performance, mid-range and low cost application. Xilinx also offers some special grade FPGAs like space grade, defence grade and automotive grade FPGA. Some of the family are listed here.

  • Virtex – Xilinx’s high performance FPGA. It offers highest logic cells capacity that enabled by stacked silicon interconnect (SSI). The family targets for ASIC prototyping and high performance communication systems.
  • Spartan – Low cost FPGA. The family targets for high volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications . Xilinx announce the Spartan 6 series is the end of the series and has been succeed by two families – Kintex and Artix.
  • Kintex – Mid-range mixed signal FPGA. Optimized for highest performance-price ratio. The family targets for high performance signal processing, long term wireless network and 3D flat panel display.
  • Artix – Low cost mixed signal FPGA. Optimized for lowest cost and power with small form factor packaging for the highest volume applications. The family targets for medical devices, handheld devices and automation applications.
  • Feature Spartan 6 Artix 7 Kintex 7 Virtex 7
    Type SRAM based SRAM based SRAM based SRAM based
    Logic Cells 147K 360K 478K 1,955K
    Block RAM 4.8Mbit 19Mbit 34Mbit 68Mbit
    Configurable ADC - 17 channels 16 channels -
    DSP slices 180 1,040 1,920 3,600
    IO Pins 576 600 500 1,200
    PCI-e x1 Gen1, Endpoint only x4 Gen2, Root & Endpoint x8 Gen2, Root & Endpoint x8 Gen3, Root & Endpoint
    Configuration JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP JTAG, Master SPI, Master BPI, Master/Slave Serial, Master/Slave SelectMAP
    Configuration bits (x) 3Mbit<x<33Mbit haven’t release 23Mbit<x<143Mbit 107Mbit<x<427Mbit

    To synthesis a design for Xilinx’s FPGA, Xilinx offers a software pack called ISE design suite to simplify the development cycle. A free edition – ISE webpack is also available but only support limited device.

    Altera
    Similar to Xilinx, Altera offers three FPGA groups that cover high performance, mid-range and low cost application. They also supports wide temperature range for commercial, industrial, extended industrial, automotive, and military application. Three major family are listed below.

  • Stratix – Altera’s high performance FPGA family. It targets for high performance communication systems and ASIC prototyping.
  • Arria – The family targets for cost sensitive applications that require high performance computation functionality, such as digital signal processing (DSP), wireless, wireline and video end markets. Latest series also intergrates an Dual-core ARM Cortex-A9 in the same die.
  • Cyclone – The family targets for high-volume applications at the lowest cost and lowest power (compares to Stratix and Arria), such application are industrial automation, wireless, wireline, consumers and automotive.
  • Feature Cyclone V Arria V Stratix V
    Type SRAM based SRAM based SRAM based
    Logic Cells 301K 504.14K 952K
    Block RAM 11.6Mbit 24.14Mbit 52Mbit
    DSP Block 342 1,156 704
    Users IO 488 704 840
    PCI-e x4 Gen2 Root and Endpoint x8 Gen2 Root and Endpoint x8 Gen3 Root and Endpoint
    Configuration JTAG, Active Serial, Passive Serial, Fast Passive Parallel, PCIe JTAG, Active Serial, Passive Serial, Fast Passive Parallel, PCIe, Internal Hard Processor System JTAG, Active Serial, Passive Serial, Fast Passive Parallel, PCIe, Partial Reconfiguration
    Configuration bits (x) 20Mbit<x<190Mbit (some of the devices haven’t release) 66Mbit<x<177Mbit 89Mbit<x<370Mbit

    Altera offers a software development suite called Quartus II to simplify the development cycle. A free web edition is available but only support limited device.

    Lattice Semiconductor
    Lattice also focuses on SRAM based FPGA. The company offers three major FPGA groups, they are high-value, high performance and non-volatile FPGA. Lattice also offer a very low power FPGA which is known as mobileFPGA, a series of FPGA that acquires from SiliconBlue.

  • SC – Lattice’s high performance FPGA. It delivers best in class solutions for high throughput standards like Ethernet, PCI Express, SPI4.2 and high speed memory controllers.
  • ECP – High-value FPGA. It’s target applications are wireline, wireless communication and video processing.
  • XP – SRAM based FPGA with internal flash memory. The architecture simplify the board level design since no external configuration flash memory is needed.
  • iCE – This family is known as mobileFPGA. It focuses on the applications that require low power, less space and less bill of materials, such as smartphones and tablets.
  • Feature iCE40 XP2 ECP4 SC
    Type SRAM based (with internal non-volatile memory) SRAM based (with internal non-volatile memory) SRAM based SRAM based
    Logic Cells 16K 40K 241K 115.2K
    Block RAM 384Kbit 885Kbit 10.62Mbit 7.8Mbit
    DSP Block - 8 576 -
    Users IO 222 540 512 942
    Configuration Master/Slave SPI (ISP or Socket Adapter) JTAG, Master/Slave SPI JTAG, Master/Slave SPI, I2C, Parallel (8bit or 16bit bus) JTAG, Master SPI, Master/Slave SPI, Master/Slave Parallel, MPI -8 -16 -32
    Configuration bits (x) 120Kbit<x<2114Kbit 1.27Mbit<x<8.03Mbit 10.7Mbit<x<54.5Mbit< 4.6Mbit<x<35.8Mbit

    Lattice also offers software design suite called Lattice Diamond. A free license is available but with limited device support.

    Microsemi (formally Actel)
    MicroSemi focuses on Flash based and one time programmable FPGA. The company splits their products into four major groups, they are low power, mixed signal, radiation tolerant and Anti-Fuse FPGA. Each group can further divides into few families. Few of the families are listed below.

  • IGLOO – Low power FPGA with integrated flash memory. It targets for portable, display and human machine interface application.
  • SmartFusion – Mixed signal FPGA. Come with hard 32-bit ARM Cortex-M3 microcontroller core, programmable analog with analog-to-digital converter (ADC), voltage/current/temperature monitors, digital-to-analog converter (DAC), comparators, and analog compute engine (ACE).
  • RT ProASIC – Re-programmable radiation tolerant FPGA. It targets for military and aerospace appications.
  • Axcelerator – High speed Anti-Fuse FPGA. It targets for consumer, industrial, medical, military and aerospace applications.
  • Feature IGLOO SmartFusion RT ProASIC3 Axcelerator
    Type Flash Based Flash Based Flash Based One Time Programmable
    Logic Cells 75,264 11,520 75,264 10,752(Register) 21,504(Combinatorial)
    Block RAM 504Kbit 108Kbit + 64MByte from ARM 444.9Kbit 294.9Kbit
    Users IO 620 128 620 684
    FlashROM bit 1024 512KByte (using ARM’s flash memory) 1000 - (Anti-Fuse)
    Programming JTAG JTAG JTAG JTAG

    MicroSemi also offers a software called Libero that integrates all the nesessary tools for FPGA. Free editions are available, but not all functions are supported. Although the numbers of logic cells are lesser than previous companies. However, the attracting points of these families are the power consumption and non-volatile logic cells.

    Some families from four major FPGA vendors are listed above. The numbers from each table are for reference only. Please refer to the datasheet for the exact parameters.

    Here are some suggestions for FPGA selection:

  • Using the vendor specific synthesis tool to synthesize the design. This should get the number of logic elements that used by the family.
  • Using the vendor specific power estimator roughly calculate the power consumption. Is that over the maximum capability of power supply?
  • Choosing the FPGA that meets your peripherals’ I/O count and logic level. More I/Os mean more power consumption and cost.
  • Choosing the FPGA that meets your design’s RAM size.
  • SRAM based, Flash based or Anti-Fuse FPGA. Difference type will result in different board level design/layout.
  • Contact your local distributer for price quotation if the cost is sensitive.
  • Check if any supporting design tools are available for the FPGA.
  • When the family/device will become obsolescence. Find the latest product may prolong the life cycle of end product.
  • Other constrains like form factor, temperature and radiation tolerant are important for some applications. Consider them if they are needed.

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