ASH1: Architecture

After summarizing USB Operations, time to kick off the ball for the match of ASH vs. IOP

The general view of ASH1 processor is as the following:

  1. ASH1 is a stack-based processor, where the majoroty of the operations will be done on a stack, this participates in reducing the instructions operands.
  2. The initial plan was to make ASH1 a multi-cycle processor but with the introduction of an instruction memory unit, ASH1 is generally a single-cycle processor with the exception for special instructions.
  3. ASH1 will be communicating with the master CPU through a set of interrupt signals and a wishbone bus which enables the master CPU to access a file of “configuration” registers, a Tx Fifo buffer, and  an Rx Fifo buffer.
  4. The control logic for ASH1 adopted the microcoded design approach. The advantage of the microcoded scheme is that it lets the designer to easily (i.e flexible) change the control logic without having to redesign the decoding circuits
  5. The major components of ASH1 are integrated and connected to each other via two buses namely; data bus (dbus) and address bus (abus)
  6. What makes ASH1 special, is that it’s designed for i/o operations. Therefore, there are some special instructions that can not be found in any other general-purpose processor, for instance CRCOP instruction is now being able to generate and check the CRC pattern for a USB packet. Another example is the NRZI/NRZL encoding/decoding instruction.

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