Power Optimisation

Since the recent LLVM 2.7 release came with initial support for the Microblaze, it is now conceivable to add some features into the LLVM to enable power optimisation for the AEMB and other architectures. The reason that LLVM is chosen instead of GCC is purely subjective – a cleaner code base and the open license adopted.

The idea of power optimisation lies behind the premise that power is a systems level problem – not a hardware one. While hardware is a large contributor, hardware cannot do anything unless it is commanded by software, which is ultimately slaved to user events. Therefore, it is unfair to place the entire power problem in the hands of the hardware designer.

One step in the right direction is to incorporate power metrics into compiler optimisation. We now have very obvious speed and size optimisation options. These flags tell the compiler to run various extra algorithms to come up with optimised code-paths that are either faster or consume less memory than the default output.

There is no reason why this cannot be extended to power optimised code.

As a simple example, let us consider a simple multiply-by-two operation. This can either be accomplished by using the hardware multiplier or by using the adder or even by using the shifter. Each functional element can be used to produce the same results from a purely mathematical standpoint.

However, each hardware block consumes very a very different power envelope. Some are simple routing devices while others are complex devices with lots of gates and transistors stuck in between. However, there are obviously trade-offs as not all these operations can complete within a single clock cycle on all architectures.

Therefore, there is room for innovation and further research in this area.

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